HD64F3644PV Datasheet, PDF (305/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 Serial Communication Interface
Bit 0Start Flag (STF): Bit 0 controls the start of a transfer. Setting this bit to 1 causes SCI1 to
start transferring data.
During the transfer or while waiting for the first clock pulse, this bit remains set to 1. It is cleared
to 0 upon completion of the transfer. It can therefore be used as a busy flag.
Bit 0: STF
0
1
Description
Read: Indicates that transfer is stopped
Write: Invalid
Read: Indicates transfer in progress
Write: Starts a transfer operation
(initial value)
Serial Data Register U (SDRU)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
SDRU7 SDRU6 SDRU5 SDRU4 SDRU3 SDRU2 SDRU1 SDRU0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SDRU is an 8-bit read/write register. It is used as the data register for the upper 8 bits in 16-bit
transfer (SDRL is used for the lower 8 bits).
Data written to SDRU is output to SDRL starting from the least significant bit (LSB). This data is
then replaced by LSB-first data input at pin SI1, which is shifted in the direction from the most
significant bit (MSB) toward the LSB.
SDRU must be written or read only after data transmission or reception is complete. If this register
is written or read while a data transfer is in progress, the data contents are not guaranteed.
The SDRU value upon reset is undefined.
Serial Data Register L (SDRL)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
SDRL7 SDRL6 SDRL5 SDRL4 SDRL3 SDRL2 SDRL1 SDRL0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 6.00 Sep 12, 2006 page 283 of 526
REJ09B0326-0600