HD64F3644PV Datasheet, PDF (264/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 Timers
9.5.2 Register Descriptions
Free-Running Counter (FRC)
Free-Running Counter H (FRCH)
Free-Running Counter L (FRCL)
FRC
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value
Read/Write
0000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
FRCH
FRCL
FRC is a 16-bit read/write up-counter, which is incremented by internal or external clock input.
The clock source is selected by bits CKS1 and CKS0 in TCRX.
FRC can be cleared by compare match A, depending on the setting of CCLRA in TCSRX.
When FRC overflows from H'FFFF to H'0000, OVF is set to 1 in TCSRX. If OVIE = 1 in TIER, a
CPU interrupt is requested.
FRC can be written and read by the CPU. Since FRC has 16 bits, data is transferred between the
CPU and FRC via a temporary register (TEMP). For details see section 9.5.3, CPU Interface.
FRC is initialized to H'0000 upon reset and in standby mode, watch mode, subsleep mode, and
subactive mode.
Output Compare Registers A and B (OCRA, OCRB)
Output Compare Registers AH and BH (OCRAH, OCRBH)
Output Compare Registers AL and BL (OCRAL, OCRBL)
OCRA, OCRB
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value
Read/Write
1111111111111111
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
OCRAH, OCRBH
OCRAL, OCRBL
Rev. 6.00 Sep 12, 2006 page 242 of 526
REJ09B0326-0600