HD64F3644PV Datasheet, PDF (308/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 Serial Communication Interface
6. After data reception is complete, an overrun occurs if the serial clock continues to be input; no
data is received and the SCSR1 overrun error flag (bit ORER) is set to 1.
Simultaneous Transmit/Receive: A simultaneous transmit/receive operation is carried out as
follows.
1. Set bits SO1, SI1, and SCK1 to 1 in PMR3 to select the SO₁, SI₁, and SCK₁ pin functions. If
necessary, set bit POF1 in PMR7 for NMOS open-drain output at pin SO₁.
2. Clear bit SNC1 in SCR1 to 0, set bit SNC0 to 0 or 1, and clear bit MRKON to 0, designating
8- or 16-bit synchronous transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing
data to SCR1 when bit MRKON in SCR1 is cleared to 0 initializes the internal state of SCI1.
3. Write transmit data in SDRL and SDRU, as follows.
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
4. Set the SCSR1 start flag (STF) to 1. SCI1 starts operating. Transmit data is output at pin SO₁.
Receive data is input at pin SI₁.
5. After data transmission and reception are complete, bit IRRS1 in IRR2 is set to 1.
6. Read the received data from SDRL and SDRU, as follows.
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
When an internal clock is used, a serial clock is output from pin SCK₁ in synchronization with the
transmit data. After data transmission is complete, the serial clock is not output until the next time
the start flag is set to 1. During this time, pin SO₁ continues to output the value of the last bit
transmitted.
When an external clock is used, data is transmitted and received in synchronization with the serial
clock input at pin SCK₁. After data transmission and reception are complete, an overrun occurs if
the serial clock continues to be input; no data is transmitted or received and the SCSR1 overrun
error flag (bit ORER) is set to 1.
While transmission is stopped, the output value of pin SO₁ can be changed by rewriting bit SOL in
SCSR1.
Rev. 6.00 Sep 12, 2006 page 286 of 526
REJ09B0326-0600