HD64F3644PV Datasheet, PDF (118/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 5 Power-Down Modes
5.3.3 Oscillator Settling Time after Standby Mode Is Cleared
Bits STS2 to STS0 in SYSCR1 should be set as follows.
• When a crystal oscillator is used
The table 5.4 gives settings for various operating frequencies. Set bits STS2 to STS0 for a
waiting time of at least 10 ms.
Table 5.4 Clock Frequency and Settling Time (times are in ms)
STS2 STS1 STS0 Waiting Time 5 MHz 4 MHz 2 MHz 1 MHz 0.5 MHz
0
0
0
8,192 states
1.6
2.0
4.1
8.2
16.4
0
0
1
16,384 states 3.2
4.1
8.2
16.4
32.8
0
1
0
32,768 states 6.6
8.2
16.4
32.8
65.5
0
1
1
65,536 states
13.1
16.4
32.8
65.5
131.1
1
*
*
Legend: * Don’t care
131,072 states 26.2
32.8
65.5
131.1 262.1
• When an external clock is used
Any values may be set. Normally the minimum time (STS2 = STS1 = STS0 = 0) should be set.
5.4 Watch Mode
5.4.1 Transition to Watch Mode
The system goes from active or subactive mode to watch mode when a SLEEP instruction is
executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1.
In watch mode, operation of on-chip peripheral modules other than timer A is halted. As long as a
minimum required voltage is applied, the contents of CPU registers, the on-chip RAM and some
registers of the on-chip peripheral modules, are retained. I/O ports keep the same states as before
the transition.
Rev. 6.00 Sep 12, 2006 page 96 of 526
REJ09B0326-0600