HD64F3644PV Datasheet, PDF (241/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 Timers
Timer Control Register V0 (TCRV0)
Bit
Initial value
Read/Write
7
CMIEB
0
R/W
6
CMIEA
0
R/W
5
OVIE
0
R/W
4
CCLR1
0
R/W
3
CCLR0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
TCRV0 is an 8-bit read/write register that selects the TCNTV input clock, controls the clearing of
TCNTV, and enables interrupts.
TCRV0 is initialized to H'00 upon reset and in standby mode, watch mode, subsleep mode, and
subactive mode.
Bit 7Compare Match Interrupt Enable B (CMIEB): Bit 7 enables or disables the interrupt
request (CMIB) generated from CMFB when CMFB is set to 1 in TCSRV.
Bit 7: CMIEB
0
1
Description
Interrupt request (CMIB) from CMFB disabled
Interrupt request (CMIB) from CMFB enabled
(initial value)
Bit 6Compare Match Interrupt Enable A (CMIEA): Bit 6 enables or disables the interrupt
request (CMIA) generated from CMFA when CMFA is set to 1 in TCSRV.
Bit 6: CMIEA
0
1
Description
Interrupt request (CMIA) from CMFA disabled
Interrupt request (CMIA) from CMFA enabled
(initial value)
Bit 5Timer Overflow Interrupt Enable (OVIE): Bit 5 enables or disables the interrupt
request (OVI) generated from OVF when OVF is set to 1 in TCSRV.
Bit 5: OVIE
0
1
Description
Interrupt request (OVI) from OVF disabled
Interrupt request (OVI) from OVF enabled
(initial value)
Bits 4 and 3Counter Clear 1 and 0 (CCLR1, CCLR0): Bits 4 and 3 specify whether or not to
clear TCNTV, and select compare match A or B or an external reset input.
When clearing is specified, if TRGE is set to 1 in TCRV1, then when TCNTV is cleared it is also
halted. Counting resumes when a trigger edge is input at the TRGV pin.
Rev. 6.00 Sep 12, 2006 page 219 of 526
REJ09B0326-0600