HD64F3644PV Datasheet, PDF (377/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Start
Set A/D conversion speed
and input channels
Enable A/D conversion
end interrupt
Start A/D conversion
Section 12 A/D Converter
A/D conversion
end interrupt?
No
Yes
Clear bit IRRAD to
0 in IRR2
Read ADRR data
Yes
Perform A/D
conversion?
No
End
Figure 12.5 Flow Chart of Procedure for Using A/D Converter (2) (Interrupts Used)
12.6 Application Notes
• Data in the A/D result register (ADRR) should be read only when the A/D start flag (ADSF) in
the A/D start register (ADSR) is cleared to 0.
• Changing the digital input signal at an adjacent pin during A/D conversion may adversely
affect conversion accuracy.
Rev. 6.00 Sep 12, 2006 page 355 of 526
REJ09B0326-0600