HD64F3644PV Datasheet, PDF (490/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
TCRV0—Timer control register V0
H'FFB8
Timer V
Bit
Initial value
Read/Write
7
CMIEB
0
R/W
6
CMIEA
0
R/W
5
OVIE
0
R/W
4
3
CCLR1 CCLR0
0
0
R/W R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Clock select
TCRV0
TCRV1
Bit 2 Bit 1 Bit 0 Bit 0
CKS2 CKS1 CKS0 ICKS0
Description
0 0 0 — Clock input disabled
1 0 Internal clock: φ/4, falling edge
1 Internal clock: φ/8, falling edge
1 0 0 Internal clock: φ/16, falling edge
1 Internal clock: φ/32, falling edge
1 0 Internal clock: φ/64, falling edge
1 Internal clock: φ/128, falling edge
1 0 0 — Clock input disabled
1 — External clock: rising edge
1 0 — External clock: falling edge
1 — External clock: rising and falling edges
Counter clear 1 and 0
0 0 Clearing is disabled
1 Cleared by compare match A
1 0 Cleared by compare match B
1 Cleared by rising edge of external reset input
Timer overflow interrupt enable
0 Interrupt request (OVI) from OVF disabled
1 Interrupt request (OVI) from OVF enabled
Compare match interrupt enable A
0 Interrupt request (CMIA) from CMFA disabled
1 Interrupt request (CMIA) from CMFA enabled
Compare match interrupt enable B
0 Interrupt request (CMIB) from CMFB disabled
1 Interrupt request (CMIB) from CMFB enabled
Rev. 6.00 Sep 12, 2006 page 468 of 526
REJ09B0326-0600