HD64F3644PV Datasheet, PDF (322/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 Serial Communication Interface
Serial Status Register (SSR)
Bit
7
6
5
4
TDRE RDRF OER FER
Initial value
1
0
0
0
Read/Write
R/(W)^* R/(W)^* R/(W)^* R/(W)^*
Note: * Only a write of 0 for flag clearing is possible.
3
PER
0
R/(W)^*
2
TEND
1
R
1
MPBR
0
R
0
MPBT
0
R/W
SSR is an 8-bit register containing status flags that indicate the operational status of SCI3, and
multiprocessor bits.
SSR can be read or written by the CPU at any time, but only a write of 1 is possible to bits TDRE,
RDRF, OER, PER, and FER. In order to clear these bits by writing 0, 1 must first be read.
Bits TEND and MPBR are read-only bits, and cannot be modified.
SSR is initialized to H'84 upon reset, and in standby, watch, subactive, or subsleep mode.
Bit 7Transmit Data Register Empty (TDRE): Bit 7 indicates that transmit data has been
transferred from TDR to TSR.
Bit 7: TDRE
0
1
Description
Transmit data written in TDR has not been transferred to TSR
Clearing conditions:
• After reading TDRE = 1, cleared by writing 0 to TDRE
• When data is written to TDR by an instruction
Transmit data has not been written to TDR, or transmit data written in TDR has
been transferred to TSR
Setting conditions:
• When bit TE in SCR3 is cleared to 0
• When data is transferred from TDR to TSR
(initial value)
Rev. 6.00 Sep 12, 2006 page 300 of 526
REJ09B0326-0600