HD64F3644PV Datasheet, PDF (303/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 Serial Communication Interface
Bits 2 to 0Clock Select (CKS2 to CKS 0): When CKS3 = 0, bits 2 to 0 select the prescaler
division ratio and the serial clock cycle.
Bit 2: CKS2
0
1
Bit 1: CKS1
0
1
0
1
Bit 0: CKS0
0
1
0
1
0
1
0
1
Prescaler Division
φ/1024 (initial value)
φ/256
φ/64
φ/32
φ/16
φ/8
φ/4
φ/2
Serial Clock Cycle
φ = 5 MHz φ = 2.5 MHz
204.8 µs
409.6 µs
51.2 µs
102.4 µs
12.8 µs
25.6 µs
6.4 µs
12.8 µs
3.2 µs
6.4 µs
1.6 µs
3.2 µs
0.8 µs
1.6 µs

0.8 µs
Serial Control/Status Register 1 (SCSR1)
Bit
Initial value
Read/Write
7
6
5
4
3

SOL ORER


1
0
0
1
1

R/W R/(W)^*


Note: * Only a write of 0 for flag clearing is possible.
2
1
0

MTRF STF
1
0
0

R
R/W
SCSR1 is an 8-bit register indicating operation status and error status.
Upon reset, SCSR1 is initialized to H'9C.
Bit 7Reserved Bit: Bit 7 is reserved; it is always read as 1, and cannot be modified.
Rev. 6.00 Sep 12, 2006 page 281 of 526
REJ09B0326-0600