HD64F3644PV Datasheet, PDF (116/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 5 Power-Down Modes
Bits 1 and 0 Subactive Mode Clock Select (SA1 and SA0): These bits select the CPU clock
rate (φ_W/2, φ_W/4, or φ_W/8) in subactive mode. SA1 and SA0 cannot be modified in subactive mode.
Bit 1: SA1
Bit 0: SA0
0
0
1
1
*
Legend: * Don’t care
Description
φW/8
φW/4
φW/2
(initial value)
5.2 Sleep Mode
5.2.1 Transition to Sleep Mode
Transition to Sleep (High-Speed) Mode: The system goes from active mode to sleep (high-
speed) mode when a SLEEP instruction is executed while the SSBY and LSON bits in SYSCR1
and the MSON and DTON bits in SYSCR2 are all cleared to 0. In sleep (high-speed) mode CPU
operation is halted but the on-chip peripheral functions other than PWM are operational. CPU
register contents are retained.
Transition to Sleep (Medium-Speed) Mode: The system goes from active mode to sleep
(medium-speed) mode when a SLEEP instruction is executed while the SSBY and LSON bits in
SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in SYSCR2 is
cleared to 0. In sleep (medium-speed) mode, as in sleep (high-speed) mode, CPU operation is
halted but the on-chip peripheral functions other than PWM are operational. The clock frequency
in sleep (medium-speed) mode is determined by the MA1 and MA0 bits in SYSCR1. CPU register
contents are retained.
5.2.2 Clearing Sleep Mode
Sleep mode is cleared by any interrupt (timer A, timer B1, timer X, timer V, IRQ₃ to IRQ₀, INT₇
to INT₀, SCI₃, SCI₁, or A/D converter), or by input at the RES pin.
• Clearing by interrupt
When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts.
A transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep
(medium-speed) mode to active (medium-speed) mode. Sleep mode is not cleared if the I bit of
the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the
interrupt enable register.
Rev. 6.00 Sep 12, 2006 page 94 of 526
REJ09B0326-0600