HD64F3644PV Datasheet, PDF (310/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 Serial Communication Interface
TAIL MARK: TAIL MARK can be either HOLD TAIL or LATCH TAIL. The output
waveforms of HOLD TAIL and LATCH TAIL are shown in figure 10.5. Time t in the figure is
determined by the transfer clock cycle set in bits CKS2 to CKS0 in SCR1.
< HOLD TAIL >
< LATCH TAIL >
SCK₁
SCK₁
t t t 2t t
tt
t t t 2t t
t
SO_{1 Bit 14 Bit 15}
Bit 0 ^SO1 Bit 14 Bit 15
Figure 10.5 HOLD TAIL and LATCH TAIL Waveforms
Transmitting: A transmit operation is carried out as follows.
1. Set bit SOL in SCSR1 to 1.
2. Set bits SO1 and SCK1 to 1 in PMR3 to select the S0₁ and SCK₁ pin functions. Set bit POF1 in
PMR7 to 1 for NMOS open-drain output at pin SO₁.
3. Clear bit SNC1 in SCR1 to 0 and set bit SNC0 to 0 or 1, designating 8-bit mode or 16-bit
mode. Set bit MRKON in SCR1 to 1, selecting SSB mode.
4. Write transmit data in SDRL and SDRU as follows, and select TAIL MARK with bit LTCH in
SCR1.
8-bit mode: SDRL
16-bit mode: Upper byte in SDRU, lower byte in SDRL
5. Set the SCSR1 start flag (STF) to 1. SCI1 starts operating and outputs transmit data at pin S0₁.
6. After 8- or 16-bit data transmission is complete, bit STF in SCSR1 is cleared to 0 and bit
IRRS1 in interrupt request register 2 (IRRS2) is set to 1. The selected TAIL MARK is output
after the data transmission. During TAIL MARK output, bit MTRF in SCSR1 is set to 1.
Data can be sent continuously by repeating steps 4 to 6. Check that SCI1 is in the idle state before
rewriting bit MRKON in SCR1.
Rev. 6.00 Sep 12, 2006 page 288 of 526
REJ09B0326-0600