HD64F3644PV Datasheet, PDF (86/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 Exception Handling
Bit 2IRQ₂ Edge Select (IEG2): Bit 2 selects the input sensing of pin IRQ₂.
Bit 2: IEG2
0
1
Description
Falling edge of IRQ2 pin input is detected
Rising edge of IRQ2 pin input is detected
(initial value)
Bit 1IRQ₁ Edge Select (IEG1): Bit 1 selects the input sensing of pin IRQ₁.
Bit 1: IEG1
0
1
Description
Falling edge of IRQ1 pin input is detected
Rising edge of IRQ1 pin input is detected
(initial value)
Bit 0IRQ₀ Edge Select (IEG0): Bit 0 selects the input sensing of pin IRQ₀.
Bit 0: IEG0
0
1
Description
Falling edge of IRQ0 pin input is detected
Rising edge of IRQ0 pin input is detected
(initial value)
Interrupt Edge Select Register 2 (IEGR2)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
INTEG7 INTEG6 INTEG5 INTEG4 INTEG3 INTEG2 INTEG1 INTEG0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IEGR2 is an 8-bit read/write register, used to designate whether pins INT₇ to INT₀, and TMIB are
set to rising edge sensing or falling edge sensing. Upon reset, IEGR2 is initialized to H'00.
Bit 7INT₇ Edge Select (INTEG7): Bit 7 selects the input sensing of the INT₇ pin.
Bit 7: INTEG7
0
1
Description
Falling edge of INT7 pin input is detected
Rising edge of INT7 pin input is detected
(initial value)
Rev. 6.00 Sep 12, 2006 page 64 of 526
REJ09B0326-0600