HD64F3644PV Datasheet, PDF (370/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 12 A/D Converter
12.2 Register Descriptions
12.2.1 A/D Result Register (ADRR)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R
R
R
R
R
R
R
R
The A/D result register (ADRR) is an 8-bit read-only register for holding the results of analog-to-
digital conversion.
ADRR can be read by the CPU at any time, but the ADRR values during A/D conversion are
undefined.
After A/D conversion is complete, the conversion result is stored in ADRR as 8-bit data; this data
is held in ADRR until the next conversion operation starts.
ADRR is not cleared on reset.
12.2.2 A/D Mode Register (AMR)
Bit
Initial value
Read/Write
7
6
5
CKS TRGE

0
0
1
R/W
R/W

4
3
2
1
0

CH3
CH2
CH1
CH0
1
0
0
0
0

R/W
R/W
R/W
R/W
AMR is an 8-bit read/write register for specifying the A/D conversion speed, external trigger
option, and the analog input pins.
Upon reset, AMR is initialized to H'30.
Rev. 6.00 Sep 12, 2006 page 348 of 526
REJ09B0326-0600