HD64F3644PV Datasheet, PDF (324/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 Serial Communication Interface
Bit 4Framing Error (FER): Bit 4 indicates that a framing error has occurred during reception
in asynchronous mode.
Bit 4: FER
Description
0
Reception in progress or completed^*1
(initial value)
Clearing condition:
After reading FER = 1, cleared by writing 0 to FER
1
A framing error has occurred during reception^*2
Setting condition:
When the stop bit at the end of the receive data is checked for a value of 1 at
the end of reception, and the stop bit is 0^*2
Notes: 1. When bit RE in SCR3 is cleared to 0, bit FER is not affected and retains its previous
state.
2. Note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the
second stop bit is not checked. When a framing error occurs the receive data is
transferred to RDR but bit RDRF is not set. Reception cannot be continued with bit FER
set to 1. In synchronous mode, neither transmission nor reception is possible when bit
FER is set to 1.
Bit 3Parity Error (PER): Bit 3 indicates that a parity error has occurred during reception with
parity added in asynchronous mode.
Bit 3: PER
Description
0
Reception in progress or completed^*1
(initial value)
Clearing condition:
After reading PER = 1, cleared by writing 0 to PER
1
A parity error has occurred during reception^*2
Setting condition:
When the number of 1 bits in the receive data plus parity bit does not match the
parity designated by bit PM in the serial mode register (SMR)
Notes: 1. When bit RE in SCR3 is cleared to 0, bit PER is not affected and retains its previous
state.
2. Receive data in which it a parity error has occurred is still transferred to RDR, but bit
RDRF is not set. Reception cannot be continued with bit PER set to 1. In synchronous
mode, neither transmission nor reception is possible when bit PER is set to 1.
Rev. 6.00 Sep 12, 2006 page 302 of 526
REJ09B0326-0600