HD64F3644PV Datasheet, PDF (161/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Flowchart for Erasing Multiple Blocks
Section 6 ROM
Start
Set erase block register
(set bit for block to be erased to 1)
Write 0 data in all addresses to be
erased (prewrite)^*1
n=1
Erase-verify
next block
Enable watchdog timer ^*2
Select erase mode
(E bit = 1 in FLMCR)
Wait (x) ms ^*5
Clear E bit
Erasing halts
Disable watchdog timer
Select erase-verify mode
(EV bit = 1 in FLMCR)
Wait (tvs1) µs ^*6
Set block start address as
verify address
Dummy write to verify address ^*3
(flash memory latches
address)
Wait (tvs2) µs ^*6
Notes: 1. Program all addresses to be erased by
following the prewrite flowchart.
2. Set the timer overflow interval to the initial
value shown in table 6.13.
3. For the erase-verify dummy write, write
H'FF using a byte transfer instruction.
4. For the erase-verify operation, read the
data using a byte transfer instruction.
When erasing multiple blocks, clear the
erase block register bits for erased blocks
and perform additional erasing only for
unerased blocks.
5. Erase time x is successively incremented
to initial set value × 2^n–1 (n = 1 to 4), and
is fixed from the 4th time onward. An initial
value of 6.25 ms or less should be set,
and the time for one erasure should be 50
ms or less.
6. tvs1: 4 µs or more
tvs2: 2 µs or more
N: 602 (set N so that the total erase
time does not exceed 30 s)
Address + 1 → address
Verify ^*4
(read data H'FF?)
OK
No
Last address
of block?
Yes
Clear EBR bit for erase
block
No
Erase-verify
completed for all erase
blocks?
Yes
Clear EV bit
All erase
blocks erased?
(EBR1 = EBR2 = 0?)
Yes
End of erase
NG
Erase-verify next block
Erase-verify
No
completed for all erase
blocks?
Yes
n+1→n
n ≥ 4?
Yes
No
Double the erase time
(x × 2 → x)
No
n ≥ N? ^*6
No
Yes
Erase error
Figure 6.16 Multiple-Block Erase Flowchart
Rev. 6.00 Sep 12, 2006 page 139 of 526
REJ09B0326-0600