HD64F3644PV Datasheet, PDF (243/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Timer Control/Status Register V (TCSRV)
Bit
7
6
5
4
3
CMFB CMFA OVF

OS3
Initial value
0
0
0
1
0
Read/Write
R/(W)^* R/(W)^* R/(W)^*

R/W
Note: * Bits 7 to 5 can be only written with 0, for flag clearing.
Section 9 Timers
2
OS2
0
R/W
1
OS1
0
R/W
0
OS0
0
R/W
TCSRV is an 8-bit register that sets compare match flags and the timer overflow flag, and controls
compare match output.
TCSRV is initialized to H'10 upon reset and in standby mode, watch mode, subsleep mode, and
subactive mode.
Bit 7Compare Match Flag B (CMFB): Bit 7 is a status flag indicating that TCNTV has
matched TCORB. This flag is set by hardware and cleared by software. It cannot be set by
software.
Bit 7: CMFB
0
1
Description
Clearing condition:
After reading CMFB = 1, cleared by writing 0 to CMFB
Setting condition:
Set when the TCNTV value matches the TCORB value
(initial value)
Bit 6Compare Match Flag A (CMFA): Bit 6 is a status flag indicating that TCNTV has
matched TCORA. This flag is set by hardware and cleared by software. It cannot be set by
software.
Bit 6: CMFA
0
1
Description
Clearing condition:
After reading CMFA = 1, cleared by writing 0 to CMFA
Setting condition:
Set when the TCNTV value matches the TCORA value
(initial value)
Rev. 6.00 Sep 12, 2006 page 221 of 526
REJ09B0326-0600