HD64F3644PV Datasheet, PDF (325/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 Serial Communication Interface
Bit 2Transmit End (TEND): Bit 2 indicates that bit TDRE is set to 1 when the last bit of a
transmit character is sent.
Bit 2 is a read-only bit and cannot be modified.
Bit 2: TEND
0
1
Description
Transmission in progress
Clearing conditions:
• After reading TDRE = 1, cleared by writing 0 to TDRE
• When data is written to TDR by an instruction
Transmission ended
(initial value)
Setting conditions:
• When bit TE in SCR3 is cleared to 0
• When bit TDRE is set to 1 when the last bit of a transmit character is sent
Bit 1Multiprocessor Bit Receive (MPBR): Bit 1 stores the multiprocessor bit in a receive
character during multiprocessor format reception in asynchronous mode.
Bit 1 is a read-only bit and cannot be modified.
Bit 1: MPBR
Description
0
Data in which the multiprocessor bit is 0 has been received^*
(initial value)
1
Data in which the multiprocessor bit is 1 has been received
Note: * When bit RE is cleared to 0 in SCR3 with the multiprocessor format, bit MPBR is not
affected and retains its previous state.
Bit 0Multiprocessor Bit Transfer (MPBT): Bit 0 stores the multiprocessor bit added to
transmit data when transmitting in asynchronous mode. The bit MPBT setting is invalid when
synchronous mode is selected, when the multiprocessor communication function is disabled, and
when not transmitting.
Bit 0: MPBT
0
1
Description
A 0 multiprocessor bit is transmitted
A 1 multiprocessor bit is transmitted
(initial value)
Rev. 6.00 Sep 12, 2006 page 303 of 526
REJ09B0326-0600