HD64F3644PV Datasheet, PDF (328/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 Serial Communication Interface
Notes: 1. The setting should be made so that the error is not more than 1%.
2. The value set in BRR is given by the following equation:
N=
OSC
(64 × 2²ⁿ × B)
× 10⁶ – 1
where
B: Bit rate (bit/s)
N: Baud rate generator BRR setting (0 ≤ N ≤ 255)
OSC: Value of φ_OSC (MHz)
n: Baud rate generator input clock number (n = 0, 1, 2, or 3)
(The relation between n and the clock is shown in table 10.7.)
Table 10.7 Relation between n and Clock
n
Clock
CKS1
0
φ
0
1
φ/4
0
2
φ16
1
3
φ/64
1
SMR Setting
CKS0
0
1
0
1
3. The error in table 10.6 is the value obtained from the following equation, rounded to
two decimal places.
Error (%) = ^{B (rate obtained from n, N, OSC) – R (bit rate in left-hand column in table 10.6)} × 100
R (bit rate in left-hand column in table 10.6)
Rev. 6.00 Sep 12, 2006 page 306 of 526
REJ09B0326-0600