HD64F3644PV Datasheet, PDF (269/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 Timers
Timer Control/Status Register X (TCSRX)
Bit
7
6
5
4
3
ICFA ICFB ICFC ICFD OCFA
Initial value
0
0
0
0
0
Read/Write
R/(W)^* R/(W)^* R/(W)^* R/(W)^* R/(W)^*
Note: * Bits 7 to 1 can only be written with 0 for flag clearing.
2
OCFB
0
R/(W)^*
1
OVF
0
R/(W)^*
0
CCLRA
0
R/W
TCSRX is an 8-bit register that selects clearing of the counter and controls interrupt request
signals.
TCSRX is initialized to H'00 upon reset and in standby mode, watch mode, subsleep mode, and
subactive mode. Other timing is described in section 9.6.3, Timer Operation.
Bit 7Input Capture Flag A (ICFA): Bit 7 is a status flag that indicates that the FRC value has
been transferred to ICRA by an input capture signal. If BUFEA is set to 1 in TCRX, ICFA
indicates that the FRC value has been transferred to ICRA by an input capture signal and that the
ICRA value before this update has been transferred to ICRC.
This flag is set by hardware and cleared by software. It cannot be set by software.
Bit 7: ICFA
0
1
Description
Clearing condition:
After reading ICFA = 1, cleared by writing 0 to ICFA
(initial value)
Setting condition:
Set when the FRC value is transferred to ICRA by an input capture signal
Bit 6Input Capture Flag B (ICFB): Bit 6 is a status flag that indicates that the FRC value has
been transferred to ICRB by an input capture signal. If BUFEB is set to 1 in TCRX, ICFB
indicates that the FRC value has been transferred to ICRB by an input capture signal and that the
ICRB value before this update has been transferred to ICRC.
This flag is set by hardware and cleared by software. It cannot be set by software.
Bit 6: ICFB
0
1
Description
Clearing condition:
After reading ICFB = 1, cleared by writing 0 to ICFB
(initial value)
Setting condition:
Set when the FRC value is transferred to ICRB by an input capture signal
Rev. 6.00 Sep 12, 2006 page 247 of 526
REJ09B0326-0600