HD64F3644PV Datasheet, PDF (48/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 2 CPU
Table 2.2 Effective Address Calculation
Addressing Mode and
No. Instruction Format
1
Register indirect, Rn
Effective Address
Calculation Method
15
87 43 0
op
rm rn
2
Register indirect, @Rn
15
op
76 43 0
rm
15
0
Contents (16 bits) of
register indicated by rm
3
Register indirect with
displacement, @(d:16, Rn)
15
0
Contents (16 bits) of
register indicated by rm
15
76 43 0
op
rm
disp
disp
4
Register indirect with
post-increment, @Rn+
15
op
76 43 0
rm
15
0
Contents (16 bits) of
register indicated by rm
1 or 2
Register indirect with
pre-decrement, @–Rn
15
op
76 43 0
rm
15
0
Contents (16 bits) of
register indicated by rm
Incremented or
decremented by 1 if
operand is byte size, ^{1 or 2}
and by 2 if word size
Effective Address (EA)
3
03
0
rm
rn
Operand is contents of
registers indicated by rm/rn
15
0
15
0
15
0
15
0
Rev. 6.00 Sep 12, 2006 page 26 of 526
REJ09B0326-0600