HD64F3644PV Datasheet, PDF (91/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 Exception Handling
Bits 3 to 0IRQ₃ to IRQ₀ Interrupt Request Flags (IRRI3 to IRRI0)
Bit n: IRRIn
0
1
Description
Clearing condition:
When IRRIn = 1, it is cleared by writing 0
(initial value)
Setting condition:
When pin IRQn is designated for interrupt input and the designated signal edge
is input
(n = 3 to 0)
Interrupt Request Register 2 (IRR2)
Bit
7
6
5
4
3
2
1
0
IRRDT IRRAD

IRRS1




Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W^* R/W^*

R/W^*




Note: * Only a write of 0 for flag clearing is possible.
IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct
transfer, A/D converter, or SCI1 interrupt is requested. The flags are not cleared automatically
when an interrupt is accepted. It is necessary to write 0 to clear each flag. Upon reset, IRR2 is
initialized to H'00.
Bit 7Direct Transfer Interrupt Request Flag (IRRDT)
Bit 7: IRRDT
0
1
Description
Clearing condition:
When IRRDT = 1, it is cleared by writing 0
(initial value)
Setting condition:
When a direct transfer is made by executing a SLEEP instruction while DTON
= 1 in SYSCR2
Bit 6A/D Converter Interrupt Request Flag (IRRAD)
Bit 6: IRRAD
0
1
Description
Clearing condition:
When IRRAD = 1, it is cleared by writing 0
(initial value)
Setting condition:
When A/D conversion is completed and ADSF is cleared to 0 in ADSR
Rev. 6.00 Sep 12, 2006 page 69 of 526
REJ09B0326-0600