HD64F3644PV Datasheet, PDF (266/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 Timers
external input signal can be selected simultaneously, by setting IEDGA ≠ IEDGC. If IEDGA =
IEDGC, then only one edge is selected (either the rising edge or falling edge). See table 9.16.
Note: The FRC value is transferred to the input capture register (ICR) regardless of the value of
the input capture flag (ICF).
IEOGA BUFEA IEDGC
FTIA
Edge detector
and internal
capture signal
generator
ICRC
ICRA
FRC
Figure 9.17 Buffer Operation (Example)
Table 9.16 Input Edge Selection during Buffer Operation
IEDGA
0
1
IEDGC
0
1
0
1
Input Edge Selection
Falling edge of input capture A input signal is captured (initial value)
Rising and falling edge of input capture A input signal are both captured
Rising edge of input capture A input signal is captured
ICRA to ICRD can be written and read by the CPU. Since they are 16-bit registers, data is
transferred from them to the CPU via a temporary register (TEMP). For details see section 9.5.3,
CPU Interface.
To assure input capture, the pulse width of the input capture input signal must be at least 1.5
system clocks (φ) when a single edge is selected, or at least 2.5 system clocks (φ) when both edges
are selected.
ICRA to ICRD are initialized to H'0000 upon reset and in standby mode, watch mode, subsleep
mode, and subactive mode.
Rev. 6.00 Sep 12, 2006 page 244 of 526
REJ09B0326-0600