HD64F3644PV Datasheet, PDF (287/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 Timers
9.5.8 Application Notes
The following types of contention can occur in timer X operation.
1. Contention between FRC write and counter clear
If an FRC clear signal is generated in the T₃ state of a write cycle to the lower byte of FRC,
clearing takes precedence and the write to the counter is not carried out. Figure 9.32 shows the
timing.
FRC lower byte write cycle
T₁
T₂
T₃
φ
Address
FRC address
Internal write
signal
Counter clear
signal
FRC
N
H'0000
Figure 9.32 Contention between FRC Write and Clear
Rev. 6.00 Sep 12, 2006 page 265 of 526
REJ09B0326-0600