HD64F3644PV Datasheet, PDF (512/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
IRR3—Interrupt request register 3
H'FFF9
System control
Bit
Initial value
Read/Write
7
INTF7
0
R/W^*
6
INTF6
0
R/W^*
5
INTF5
0
R/W^*
4
INTF4
0
R/W
3
INTF3
0
R/W ^*
2
INTF2
0
R/W^*
1
INTF1
0
R/W ^*
0
INTF0
0
R/W^*
INT₇ to INT₀ interrupt request flag
0 [Clearing condition]
When INTF_n = 1, it is cleared by writing 0
1 [Setting condition]
When the designated signal edge is input at pin INT_n
(n = 7 to 0)
Note: * Only a write of 0 for flag clearing is possible.
Rev. 6.00 Sep 12, 2006 page 490 of 526
REJ09B0326-0600