HD64F3644PV Datasheet, PDF (184/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 ROM
t_OSC1
φ
3.0 to 5.5 V
V_CC
12 ±0.6 V
V_CC + 2 V to 11.4 V
V_CCV
V_PP
(boot mode)
0 µs min.
12 ±0.6 V
V_PP
V_CCV
(user program
mode)
RES
0 µs min.
0 µs min.
Timing of boot
program branch
to RAM space
0 to V_CCV
0 to V_CCV
Period during which flash memory access
is prohibited and V_PP flag set/clear period
Min. 10 φ cycles
(When RES is low)
Figure 6.23 V_PP Power-On and Cut-Off Timing
6. Do not apply 12 V to the FV_PP pin during normal operation.
To prevent erroneous programming or erasing due to program runaway, etc., apply 12 V to the
FV_PP pin only when programming or erasing flash memory. If overprogramming or
overerasing occurs due to program runaway, etc., the memory cells may not operate normally.
A system configuration in which a high level is constantly applied to the FV_PP pin should be
avoided. Also, while a high level is applied to the FV_PP pin, the watchdog timer should be
activated to prevent overprogramming or overerasing due to program runaway, etc.
Rev. 6.00 Sep 12, 2006 page 162 of 526
REJ09B0326-0600