HD64F3644PV Datasheet, PDF (242/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 Timers
If TRGE is cleared to 0, after TCNTV is cleared it continues counting up.
Bit 4: CCLR1
0
1
Bit 3: CCLR0
0
1
0
1
Description
Clearing is disabled
Cleared by compare match A
Cleared by compare match B
Cleared by rising edge of external reset input
(initial value)
Bits 2 to 0Clock Select 2 to 0 (CKS2 to CKS0): Bits 2 to 0 and bit ICKS0 in TCRV1 select
the clock input to TCNTV.
Six internal clock sources divided from the system clock (φ) can be selected. The counter
increments on the falling edge.
If the external clock is selected, there is a further selection of incrementing on the rising edge,
falling edge, or both edges.
If TRGE is cleared to 0, after TCNTV is cleared it continues counting up.
Bit 2:
CKS2
0
TCRV0
Bit 1:
CKS1
Bit 0:
CKS0
0
0
1
1
0
1
1
0
0
1
1
0
1
TCRV1
Bit 0:
ICKS0

0
1
0
1
0
1




Description
Clock input disabled
(initial value)
Internal clock: φ/4, falling edge
Internal clock: φ/8, falling edge
Internal clock: φ/16, falling edge
Internal clock: φ/32, falling edge
Internal clock: φ/64, falling edge
Internal clock: φ/128, falling edge
Clock input disabled
External clock: rising edge
External clock: falling edge
External clock: rising and falling edges
Rev. 6.00 Sep 12, 2006 page 220 of 526
REJ09B0326-0600