HD64F3644PV Datasheet, PDF (90/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 Exception Handling
Interrupt Request Register 1 (IRR1)
Bit
7
6
5
4
IRRTB1 IRRTA


Initial value
0
0
0
1
Read/Write
R/W^* R/W^*


Note: * Only a write of 0 for flag clearing is possible.
3
IRRI3
0
R/W^*
2
IRRI2
0
R/W^*
1
IRRI1
0
R/W^*
0
IRRI0
0
R/W^*
IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer B1,
timer A, or IRQ₃ to IRQ₀ interrupt is requested. The flags are not cleared automatically when an
interrupt is accepted. It is necessary to write 0 to clear each flag. Upon reset, IRR1 is initialized to
H'10.
Bit 7Timer B1 Interrupt Request Flag (IRRTB1)
Bit 7: IRRTB1
0
1
Description
Clearing condition:
When IRRTB1 = 1, it is cleared by writing 0
Setting condition:
When the timer B1 counter value overflows from H'FF to H'00
(initial value)
Bit 6Timer A Interrupt Request Flag (IRRTA)
Bit 6: IRRTA
0
1
Description
Clearing condition:
When IRRTA = 1, it is cleared by writing 0
Setting condition:
When the timer A counter value overflows from H'FF to H'00
(initial value)
Bit 5Reserved Bit: Bit 5 is reserved: it is always read as 0 and cannot be modified.
Bit 4Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified.
Rev. 6.00 Sep 12, 2006 page 68 of 526
REJ09B0326-0600