HD64F3644PV Datasheet, PDF (88/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 Exception Handling
Bit 6Timer A Interrupt Enable (IENTA): Bit 6 enables or disables timer A overflow interrupt
requests.
Bit 6: IENTA
0
1
Description
Disables timer A interrupt requests
Enables timer A interrupt requests
(initial value)
Bit 5Reserved Bit: Bit 5 is reserved: it is always read as 0 and cannot be modified.
Bit 4Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified.
Bits 3 to 0IRQ₃ to IRQ₀ Interrupt Enable (IEN3 to IEN0): Bits 3 to 0 enable or disable IRQ₃
to IRQ₀ interrupt requests.
Bit n: IENn
0
1
Description
Disables interrupt requests from pin IRQn
Enables interrupt requests from pin IRQn
(initial value)
(n = 3 to 0)
Interrupt Enable Register 2 (IENR2)
Bit
7
6
5
4
3
2
1
0
IENDT IENAD

IENS1




Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W

R/W




IENR2 is an 8-bit read/write register that enables or disables interrupt requests. Upon reset, IENR2
is initialized to H'00.
Bit 7Direct Transfer Interrupt Enable (IENDT): Bit 7 enables or disables direct transfer
interrupt requests.
Bit 7: IENDT
0
1
Description
Disables direct transfer interrupt requests
Enables direct transfer interrupt requests
(initial value)
Rev. 6.00 Sep 12, 2006 page 66 of 526
REJ09B0326-0600