HD64F3644PV Datasheet, PDF (326/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 Serial Communication Interface
Bit Rate Register (BRR)
Bit
Initial value
Read/Write
7
BRR7
1
R/W
6
BRR6
1
R/W
5
BRR5
1
R/W
4
BRR4
1
R/W
3
BRR3
1
R/W
2
BRR2
1
R/W
1
BRR1
1
R/W
0
BRR0
1
R/W
BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud
rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR).
BRR can be read or written by the CPU at any time.
BRR is initialized to H'FF upon reset, and in standby, watch, subactive, or subsleep mode.
Table 10.6 shows examples of BRR settings in asynchronous mode. The values shown are for
active (high-speed) mode.
Table 10.6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode)
OSC (MHz)
2
2.4576
4
4.194304
Bit Rate
Error
Error
Error
Error
(bits/s) n N (%)
n N (%)
n N (%)
n N (%)
110
1 70 +0.03 1 86 +0.31 1 141 +0.03 1 148 –0.04
150
0 207 +0.16 0 255 0
1 103 +0.16 1 108 +0.21
300
0 103 +0.16 0 127 0
0 207 +0.16 0 217 +0.21
600
0 51 +0.16 0 63 0
0 103 +0.16 0 108 +0.21
1200
0 25 +0.16 0 31 0
0 51 +0.16 0 54 –0.70
2400
0 12 +0.16 0 15 0
0 25 +0.16 0 26 +1.14
4800
9600
19200
31250
38400



000

070
030
010

000
0 12 +0.16 0 13 –2.48

0 6 –2.48


010



Rev. 6.00 Sep 12, 2006 page 304 of 526
REJ09B0326-0600