HD64F3644PV Datasheet, PDF (290/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 Timers
4. Internal clock switching and counter operation
Depending on the timing, FRC may be incremented by a switch between different internal
clock sources. Table 9.19 shows the relation between internal clock switchover timing (by
writing to bits CKS1 and CKS0) and FRC operation.
When FRC is internally clocked, an increment pulse is generated from the falling edge of an
internal clock signal, which is divided from the system clock (φ). For this reason, in a case like
No. 3 in table 9.19 where the switch is from a high clock signal to a low clock signal, the
switchover is seen as a falling edge, causing FRC to increment.
FRC can also be incremented by a switch between internal and external clocks.
Table 9.19 Internal Clock Switching and FRC Operation
Clock Levels Before
and After Modifying
No. Bits CKS1 and CKS0
1 Goes from low level
to low level
FRC Operation
Clock before
switching
Clock after
switching
Count clock
2 Goes from low
to high
FRC
Clock before
switching
Clock after
switching
Count clock
N
N+1
Write to CKS1 and CKS0
FRC
N
N+1
N+2
Write to CKS1 and CKS0
Rev. 6.00 Sep 12, 2006 page 268 of 526
REJ09B0326-0600