HD64F3644PV Datasheet, PDF (245/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Timer Control Register V1 (TCRV1)
Bit
Initial value
Read/Write
7
6
5



1
1
1



Section 9 Timers
4
3
2
1
0
TVEG1 TVEG0 TRGE

ICKS0
0
0
0
1
0
R/W
R/W
R/W

R/W
TCRV1 is an 8-bit read/write register that selects the valid edge at the TRGV pin, enables TRGV
input, and selects the clock input to TCNTV.
TCRV1 is initialized to H'E2 upon reset and in watch mode, subsleep mode, and subactive mode.
Bits 7 to 5Reserved Bits: Bit 7 to 5 are reserved; they are always read as 1, and cannot be
modified.
Bits 4 and 3TRGV Input Edge Select (TVEG1, TVEG0): Bits 4 and 3 select the TRGV input
edge.
Bit 4: TVEG1
0
1
Bit 3: TVEG0
0
1
0
1
Description
TRGV trigger input is disabled
Rising edge is selected
Falling edge is selected
Rising and falling edges are both selected
(initial value)
Bit 2TRGV Input Enable (TRGE): Bit 2 enables TCNTV counting to be triggered by input at
the TRGV pin, and enables TCNTV counting to be halted when TCNTV is cleared by compare
match. TCNTV stops counting when TRGE is set to 1, then starts counting when the edge selected
by bits TVEG1 and TVEG0 is input at the TRGV pin.
Bit 2: TRGE
0
1
Description
TCNTV counting is not triggered by input at the TRGV pin, and does not stop
when TCNTV is cleared by compare match
(initial value)
TCNTV counting is triggered by input at the TRGV pin, and stops when TCNTV
is cleared by compare match
Bit 1Reserved Bit: Bit 1 is reserved; it is always read as 1, and cannot be modified.
Bit 0Internal Clock Select 0 (ICKS0): Bit 0 and bits CKS2 to CKS0 in TCRV0 select the
TCNTV clock source. For details see section 9.4.2, Register Descriptions.
Rev. 6.00 Sep 12, 2006 page 223 of 526
REJ09B0326-0600