HD64F3644PV Datasheet, PDF (254/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 Timers
9.4.7 Application Notes
The following types of contention can occur in timer V operation.
Contention between TCNTV Write and Counter Clear: If a TCNTV clear signal is generated
in the T₃ state of a TCNTV write cycle, clearing takes precedence and the write to the counter is
not carried out. Figure 9.13 shows the timing.
TCNTV write cycle by CPU
T₁
T₂
T₃
φ
Address
TCNTV address
Internal write
signal
Counter clear
signal
TCNTV
N
H'00
Figure 9.13 Contention between TCNTV Write and Clear
Rev. 6.00 Sep 12, 2006 page 232 of 526
REJ09B0326-0600