HD64F3644PV Datasheet, PDF (156/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 ROM
Prewrite Flowchart
Start
Set erase block register
(set bit for block to be programmed to 1)
Set start address ^*6
n=1
Write H'00 to flash memory
Notes: 1. Write using a byte transfer instruction.
(flash memory latches programmed address
and data) ^*1
2. For the timer overflow interval, set the
timer counter value (TCW) to H'FE.
3. In prewrite-verify mode, P, E, PV, and EV
Enable watchdog timer ^*2
are all cleared to 0, and 12 V is applied to
the VPP pin. Read using a byte transfer
Select program mode
4. Programming time x is successively
incremented to initial set value × 2^n–1
(P bit = 1 in FLMCR)
(n = 1 to 6). The initial value should
therefore be set to 15.8 µs or less to make
Wait (x) µs ^*4
the total programming time 1 ms or less.
5. tvs1: 4 µs or more
N: 6 (set N so that the total programming
Clear P bit
End of programming
time does not exceed 1 ms)
6. The start address and last address are the
start address and last address of the block
Disable watchdog timer
to be erased.
Wait (tvs1) µs ^*5
Prewrite verify ^*3
NG
(read data H'00?)
OK
Last address?
*6 _No
Yes
Clear erase block register
(clear bit for programmed block to 0)
n ≥ N? ^*5
Yes
Programming error
Double the programming time
(x × 2 → x)
n+1→n
No
Address + 1 → address
End of prewrite
Figure 6.15 Prewrite Flowchart
Rev. 6.00 Sep 12, 2006 page 134 of 526
REJ09B0326-0600