HD64F3644PV Datasheet, PDF (389/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 13 Electrical Characteristics
13.2.3 AC Characteristics (HD6473644)
Table 13.3 lists the control signal timing, and tables 13.4 and 13.5 list the serial interface timing of
the HD6473644.
Table 13.3 Control Signal Timing
V_CC = 4.0 V to 5.5 V, V_SS = 0.0 V, T_a = –20°C to +75°C, unless otherwise specified.
Item
Applicable
Values
Symbol Pins
Min Typ Max Unit Test Condition
Reference
Figure
System clock
fOSC
oscillation frequency
OSC clock (φOSC)
cycle time
tOSC
System clock (φ)
tcyc
cycle time
Subclock oscillation fW
frequency
OSC1, OSC2 2 
10 MHz VCC = 2.7 V to 5.5 V
OSC1, OSC2 100 
1000 ns
X1, X2
2
128 tOSC

25.6 µs
 32.768  kHz
VCC = 2.7 V to 5.5 V ^*1
Figure 13.1
VCC = 2.7 V to 5.5 V ^*1
VCC = 2.7 V to 5.5 V
Watch clock (φW)
cycle time
Subclock (φSUB)
cycle time
tW
X1, X2
tsubcyc
 30.5  µs VCC = 2.7 V to 5.5 V
2
8
tW VCC = 2.7 V to 5.5 V ^*2
Instruction cycle
time
Oscillation
trc
stabilization time
(crystal resonator)
2
OSC1, OSC2  

 tcyc VCC = 2.7 V to 5.5 V
tsubcyc
40 ms
60
VCC = 2.7 V to 5.5 V
Oscillation
trc
stabilization time
(ceramic resonator)
OSC1, OSC2  

20 ms
40
VCC = 2.7 V to 5.5 V
Oscillation stabilization trc
time
X1, X2

2
s
VCC = 2.7 V to 5.5 V
External clock high tCPH
width
OSC1
40 
 ns VCC = 2.7 V to 5.5 V Figure 13.1
External clock low
tCPL
width
OSC1
40 
 ns VCC = 2.7 V to 5.5 V
External clock rise
tCPr
time

15 ns VCC = 2.7 V to 5.5 V
External clock fall
tCPf
time

15 ns VCC = 2.7 V to 5.5 V
Pin RES low width
tREL
RES
10 
 tcyc VCC = 2.7 V to 5.5 V Figure 13.2
Rev. 6.00 Sep 12, 2006 page 367 of 526
REJ09B0326-0600