HD64F3644PV Datasheet, PDF (66/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 2 CPU
15
87
0
op
op
Legend:
op: Operation field
Figure 2.10 Block Data Transfer Instruction Code
2.6 Basic Operational Timing
CPU operation is synchronized by a system clock (φ) or a subclock (φ_SUB). For details on these
clock signals see section 4, Clock Pulse Generators. The period from a rising edge of φ or φ_SUB to
the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle
differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
2.6.1 Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.11 shows the on-chip memory access cycle.
φ or φ _SUB
Internal address bus
Bus cycle
T₁ state
T₂ state
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2.11 On-Chip Memory Access Cycle
Rev. 6.00 Sep 12, 2006 page 44 of 526
REJ09B0326-0600