HD64F3644PV Datasheet, PDF (511/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

IRR2—Interrupt request register 2
Bit
7
6
5
IRRDT IRRAD —
Initial value
0
0
0
Read/Write
R/W^* R/W^* —
4
IRRS1
0
R/W ^*
Appendix B Internal I/O Registers
H'FFF8
System control
3
2
1
0
—
—
—
—
0
0
0
0
—
—
—
—
SCI1 interrupt request flag
0 [Clearing condition]
When IRRS1 = 1, it is cleared by writing 0
1 [Setting condition]
When an SCI1 transfer is completed
A/D converter interrupt request flag
0 [Clearing condition]
When IRRAD = 1, it is cleared by writing 0
1 [Setting condition]
When A/D conversion is completed and ADSF is cleared to 0 in ADSR
Direct transfer interrupt request flag
0 [Clearing condition]
When IRRDT = 1, it is cleared by writing 0
1 [Setting condition]
A SLEEP instruction is executed when DTON = 1 and a direct transfer is made
Note: * Only a write of 0 for flag clearing is possible.
Rev. 6.00 Sep 12, 2006 page 489 of 526
REJ09B0326-0600