HD64F3644PV Datasheet, PDF (82/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 Exception Handling
Reset exception handling takes place as follows.
• The CPU internal state and the registers of on-chip peripheral modules are initialized, with the
I bit of the condition code register (CCR) set to 1.
• The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after
which the program starts executing from the address indicated in PC.
When system power is turned on or off, the RES pin should be held low.
Figure 3.1 shows the reset sequence starting from RES input.
RES
Reset cleared
Program initial
Vector fetch Internal ^{instruction prefetch}
processing
φ
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus (16-bit)
(1)
(2)
(2)
(3)
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) First instruction of program
Figure 3.1 Reset Sequence
Rev. 6.00 Sep 12, 2006 page 60 of 526
REJ09B0326-0600