HD64F3644PV Datasheet, PDF (199/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8.3 Port 2
8.3.1 Overview
Port 2 is a 3-bit I/O port, configured as shown in figure 8.2.
Section 8 I/O Ports
Port 2
P2 ₂ /TXD
P2 ₁ /RXD
P2 ₀ /SCK₃
Figure 8.2 Port 2 Pin Configuration
8.3.2 Register Configuration and Description
Table 8.5 shows the port 2 register configuration.
Table 8.5 Port 2 Registers
Name
Port data register 2
Port control register 2
Abbr.
R/W
PDR2
R/W
PCR2
W
Initial Value
H'00
H'00
Address
H'FFD5
H'FFE5
Port Data Register 2 (PDR2)
Bit
7
6
5
4
3
2
1
0
Initial value





P22
P21
P20
0^*
0^*
0^*
0^*
0^*
0
0
0
Read/Write





R/W
R/W
R/W
Note: * Bits 7 to 3 are reserved; they are always read as 0 and cannot be modified.
PDR2 is an 8-bit register that stores data for port 2 pins P2₂ to P2₀. If port 2 is read while PCR2
bits are set to 1, the values stored in PDR2 are read, regardless of the actual pin states. If port 2 is
read while PCR2 bits are cleared to 0, the pin states are read.
Upon reset, PDR2 is initialized to H'00.
Rev. 6.00 Sep 12, 2006 page 177 of 526
REJ09B0326-0600