HD64F3644PV Datasheet, PDF (346/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 Serial Communication Interface
Start
Read bit TDRE
1
in SSR
No
TDRE = 1?
Yes
Write transmit
data to TDR
1. Read the serial status register (SSR) and
check that bit TDRE is set to 1, then write
transmit data to the transmit data register
(TDR). When data is written to TDR, bit
TDRE is cleared to 0 automatically, the
clock is output, and data transmission is
started.
2. When continuing data transmission, be
sure to read TDRE = 1 to confirm that
a write can be performed before writing
data to TDR. When data is written to
TDR, bit TDRE is cleared to 0 automatically.
2
Continue data
Yes
transmission?
No
Read bit TEND
in SSR
No
TEND = 1?
Yes
Clear bit TE to 0
in SCR3
End
Figure 10.16 Example of Data Transmission Flowchart (Synchronous Mode)
SCI3 operates as follows when transmitting data.
SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written
to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If
bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Rev. 6.00 Sep 12, 2006 page 324 of 526
REJ09B0326-0600