HD64F3644PV Datasheet, PDF (87/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 Exception Handling
Bit 6INT₆ Edge Select (INTEG6): Bit 6 selects the input sensing of the INT₆ pin and TMIB
pin.
Bit 6: INTEG6
0
1
Description
Falling edge of INT6 and TMIB pin input is detected
Rising edge of INT6 and TMIB pin input is detected
(initial value)
Bit 5INT₅ Edge Select (INTEG5): Bit 5 selects the input sensing of the INT₅ pin and ADTRG
pin.
Bit 5: INTEG5
0
1
Description
Falling edge of INT5 and ADTRG pin input is detected
Rising edge of INT5 and ADTRG pin input is detected
(initial value)
Bits 4 to 0INT₄ to INT₀ Edge Select (INTEG4 to INTEG0): Bits 4 to 0 select the input
sensing of pins INT₄ to INT₀.
Bit n: INTEGn
0
1
Description
Falling edge of INTn pin input is detected
Rising edge of INTn pin input is detected
(initial value)
(n = 4 to 0)
Interrupt Enable Register 1 (IENR1)
Bit
Initial value
Read/Write
7
6
5
IENTB1 IENTA

0
0
0
R/W
R/W

4
3
2
1
0

IEN3 IEN2 IEN1 IEN0
1
0
0
0
0

R/W
R/W
R/W
R/W
IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Upon reset, IENR1
is initialized to H'10.
Bit 7Timer B1 Interrupt Enable (IENTB1): Bit 7 enables or disables timer B1 overflow
interrupt requests.
Bit 7: IENTB1
0
1
Description
Disables timer B1 interrupt requests
Enables timer B1 interrupt requests
(initial value)
Rev. 6.00 Sep 12, 2006 page 65 of 526
REJ09B0326-0600