HD64F3644PV Datasheet, PDF (283/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

ICRA or ICRC upper byte read cycle by CPU
T₁
T₂
T₃
φ
Section 9 Timers
FTIA
Input capture
signal
Figure 9.27 Buffered Input Capture Signal Timing (during ICRA or ICRD Read)
Input Capture Flag (ICFA to ICFD) Set Timing: Figure 9.28 shows the timing when an input
capture flag (ICFA to ICFD) is set to 1 and the FRC value is transferred to the corresponding input
capture register (ICRA to ICRD).
φ
Input capture
signal
ICFA to ICFD
FRC
ICRA to ICRD
N
N
Figure 9.28 ICFA to ICFD Set Timing
Rev. 6.00 Sep 12, 2006 page 261 of 526
REJ09B0326-0600