HD64F3644PV Datasheet, PDF (371/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 12 A/D Converter
Bit 7Clock Select (CKS): Bit 7 sets the A/D conversion speed.
Conversion Time
Bit 7: CKS
Conversion Period
φ = 2 MHz φ = 5 MHz φ = 8 MHz^*1
0
62/φ (initial value)
31 µs
12.4 µs
7.75 µs
1
31/φ
15.5 µs
^*2

Notes: 1. Applies only to F-ZTAT, R of the ZTAT, and R of the mask ROM version.
2. Operation is not guaranteed if the conversion time is less than 12.4 µs. Set bit 7 for a
value of at least 12.4 µs.
Bit 6External Trigger Select (TRGE): Bit 6 enables or disables the start of A/D conversion by
external trigger input.
Bit 6: TRGE
Description
0
Disables start of A/D conversion by external trigger
(initial value)
1
Enables start of A/D conversion by rising or falling edge of external trigger at
pin ADTRG^*
Note: * The external trigger (ADTRG) edge is selected by bit INTEG5 of IEGR2. See section
3.3.2, Interrupt Edge Select Register 2 (IEGR2) for details.
Bits 5 and 4Reserved Bits: Bits 5 and 4 are reserved; they are always read as 1, and cannot be
modified.
Rev. 6.00 Sep 12, 2006 page 349 of 526
REJ09B0326-0600