HD64F3644PV Datasheet, PDF (94/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 Exception Handling
3.3.4 Internal Interrupts
There are 21 internal interrupts that can be requested by the on-chip peripheral modules. When a
peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1.
Recognition of individual interrupt requests can be disabled by clearing the corresponding bit in
IENR1 or IENR2 to 0. All these interrupts can be masked by setting the I bit to 1 in CCR. When
internal interrupt handling is initiated, the I bit is set to 1 in CCR. Vector numbers from 23 to 9 are
assigned to these interrupts. Table 3.2 shows the order of priority of interrupts from on-chip
peripheral modules.
3.3.5 Interrupt Operations
Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the
interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance.
Interrupt controller
External or
internal
interrupts
Interrupt
request
External
interrupts or
internal
interrupt
enable
signals
I CCR (CPU)
Figure 3.2 Block Diagram of Interrupt Controller
Rev. 6.00 Sep 12, 2006 page 72 of 526
REJ09B0326-0600