HD64F3644PV Datasheet, PDF(93/551 Page) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

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HD64F3644PV Datasheet, PDF (93/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

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Section 3 Exception Handling

3.3.3 External Interrupts

There are 12 external interrupts: IRQ3 to IRQ0 and INT7 to INT0.

Interrupts IRQ3 to IRQ0: Interrupts IRQ3 to IRQ0 are requested by input signals to pins IRQ3 to

IRQ0. These interrupts are detected by either rising edge sensing or falling edge sensing,

depending on the settings of bits IEG3 to IEG0 in IEGR1.

When these pins are designated as pins IRQ3 to IRQ0 in port mode register 1 and the designated

edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt. Recognition of

these interrupt requests can be disabled individually by clearing bits IEN3 to IEN0 to 0 in IENR1.

These interrupts can all be masked by setting the I bit to 1 in CCR.

When IRQ3 to IRQ0 interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector

numbers 7 to 4 are assigned to interrupts IRQ3 to IRQ0. The order of priority is from IRQ0 (high)

to IRQ3 (low). Table 3.2 gives details.

INT Interrupts: INT interrupts are requested by input signals to pins INT7 to INT0. These

interrupts are detected by either rising edge sensing or falling edge sensing, depending on the

settings of bits INTEG7 to INTEG0 in IEGR2.

When the designated edge is input at pins INT7 to INT0, the corresponding bit in IRR3 is set to 1,

requesting an interrupt. Recognition of these interrupt requests can be disabled individually by

clearing bits INTEN7 to INTEN0 to 0 in IENR3. These interrupts can all be masked by setting the

I bit to 1 in CCR.

When INT interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector number 8 is

assigned to the INT interrupts. All eight interrupts have the same vector number, so the interrupt-

handling routine must discriminate the interrupt source.

Note: Pins INT7 to INT0 are multiplexed with port 5. Even in port usage of these pins, whenever

the designated edge is input or output, the corresponding bit INTFn is set to 1.

Rev. 6.00 Sep 12, 2006 page 71 of 526

REJ09B0326-0600

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