HD64F3644PV Datasheet, PDF (333/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 Serial Communication Interface
Table 10.12 SMR and SCR3 Settings and Clock Source Selection
SMR
Bit 7:
COM
0
1
0
1
1
SCR3
Bit 1: Bit 0:
CKE1 CKE0
0
0
1
1
0
0
0
1
0
1
1
0
1
1
1
Transmit/Receive Clock
Mode
Clock
Source SCK3 Pin Function
Asynchronous Internal
mode
I/O port (SCK3 pin not used)
Outputs clock with same frequency as
bit rate
External Inputs clock with frequency 16 times
bit rate
Synchronous
mode
Internal Outputs serial clock
External Inputs serial clock
Reserved (Do not specify these combinations)
Interrupts and Continuous Transmission/Reception: SCI3 can carry out continuous reception
using RXI and continuous transmission using TXI. These interrupts are shown in table 10.13.
Table 10.13 Transmit/Receive Interrupts
Interrupt
RXI
TXI
TEI
Flags
RDRF
RIE
TDRE
TIE
TEND
TEIE
Interrupt Request Conditions
Notes
When serial reception is performed
normally and receive data is transferred
from RSR to RDR, bit RDRF is set to 1,
and if bit RIE is set to 1 at this time, RXI
is enabled and an interrupt is requested.
(See figure 10.7 (a).)
The RXI interrupt routine reads the
receive data transferred to RDR
and clears bit RDRF to 0.
Continuous reception can be
performed by repeating the above
operations until reception of the
next RSR data is completed.
When TSR is found to be empty (on
The TXI interrupt routine writes the
completion of the previous transmission) next transmit data to TDR and
and the transmit data placed in TDR is clears bit TDRE to 0. Continuous
transferred to TSR, bit TDRE is set to 1. If transmission can be performed by
bit TIE is set to 1 at this time, TXI is
repeating the above operations until
enabled and an interrupt is requested. the data transferred to TSR has
(See figure 10.7 (b).)
been transmitted.
When the last bit of the character in TSR TEI indicates that the next transmit
is transmitted, if bit TDRE is set to 1, bit data has not been written to TDR
TEND is set to 1. If bit TEIE is set to 1 at when the last bit of the transmit
this time, TEI is enabled and an interrupt character in TSR is sent.
is requested. (See figure 10.7 (c).)
Rev. 6.00 Sep 12, 2006 page 311 of 526
REJ09B0326-0600