HD64F3644PV Datasheet, PDF (76/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 2 CPU
As a result of this operation, bit 0 in PDR3 becomes 1, and P3₀ outputs a high-level signal.
However, bits 7 and 6 of PDR3 end up with different values.
To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit
manipulation on the data in the work area, then write this data to PDR3.
[A: Prior to executing BSET]
MOV. B #80, R0L
MOV. B R0L, @RAM0
MOV. B R0L, @PDR3
The PDR3 value (H'80) is written to a work area in
memory (RAM0) as well as to PDR3.
Input/output
Pin state
PCR3
PDR3
RAM0
P37
Input
Low
level
0
1
1
P36
Input
High
level
0
0
0
P35
Output
Low
level
1
0
0
P34
Output
Low
level
1
0
0
P33
Output
Low
level
1
0
0
P32
Output
Low
level
1
0
0
P31
Output
Low
level
1
0
0
P30
Output
Low
level
1
0
0
[B: BSET instruction executed]
BSET #0 , @RAM0
The BSET instruction is executed designating the PDR3
work area (RAM0).
[C: After executing BSET]
MOV. B @RAM0, R0L
MOV. B R0L, @PDR3
The work area (RAM0) value is written to PDR3.
Input/output
Pin state
PCR3
PDR3
RAM0
P37
Input
Low
level
0
1
1
P36
Input
High
level
0
0
0
P35
Output
Low
level
1
0
0
P34
Output
Low
level
1
0
0
P33
Output
Low
level
1
0
0
P32
Output
Low
level
1
0
0
P31
Output
Low
level
1
0
0
P30
Output
High
level
1
1
1
Rev. 6.00 Sep 12, 2006 page 54 of 526
REJ09B0326-0600