HD64F3644PV Datasheet, PDF (311/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 Serial Communication Interface
10.2.5 Interrupts
SCI1 can generate an interrupt at the end of a data transfer.
When an SCI1 transfer is complete, bit IRRS1 in interrupt request register 2 (IRR2) is set to 1.
SCI1 interrupt requests can be enabled or disabled by bit IENS1 of interrupt enable register 2
(IENR2).
For further details, see section 3.3, Interrupts.
10.3 SCI3
10.3.1 Overview
Serial communication interface 3 (SCI3) can carry out serial data communication in either
asynchronous or synchronous mode. It is also provided with a multiprocessor communication
function that enables serial data to be transferred among processors.
Features
Features of SCI3 are listed below.
• Choice of asynchronous or synchronous mode for serial data communication
 Asynchronous mode
Serial data communication is performed asynchronously, with synchronization provided
character by character. In this mode, serial data can be exchanged with standard
asynchronous communication LSIs such as a Universal Asynchronous
Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter
(ACIA). A multiprocessor communication function is also provided, enabling serial data
communication among processors.
There is a choice of 12 data transfer formats.
Data length
7 or 8 bits
Stop bit length
1 or 2 bits
Parity
Even, odd, or none
Multiprocessor bit
“1” or “0”
Receive error detection
Parity, overrun, and framing errors
Break detection
Break detected by reading the RXD pin level directly when
a framing error occurs
Rev. 6.00 Sep 12, 2006 page 289 of 526
REJ09B0326-0600