MC68HC908GT16 Datasheet, PDF (98/412 Pages) Motorola, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
5.8.2 ADC Data Register
One 8-bit result register, ADC data register (ADR), is provided. This
register is updated each time an ADC conversion completes.
Address: $003D
Bit 7
6
5
4
3
2
1
Bit 0
Read: AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 5-3. ADC Data Register (ADR)
5.8.3 ADC Clock Register
The ADC clock register (ADCLK) selects the clock frequency for the
ADC.
Address: $003E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
ADIV2 ADIV1 ADIV0 ADICLK
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 5-4. ADC Clock Register (ADCLK)
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by
the ADC to generate the internal ADC clock. Table 5-2 shows the
available clock configurations. The ADC clock should be set to
approximately 1 MHz.
Technical Data
98
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
Analog-to-Digital Converter (ADC)
MOTOROLA