MC68HC908GT16 Datasheet, PDF (276/412 Pages) Motorola, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI)
SCRIE — ESCI Receive Interrupt Enable Bit
This read/write bit enables the SCRF bit to generate ESCI receiver
CPU interrupt requests. Setting the SCRIE bit in SCC2 enables the
SCRF bit to generate CPU interrupt requests. Reset clears the
SCRIE bit.
1 = SCRF enabled to generate CPU interrupt
0 = SCRF not enabled to generate CPU interrupt
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables the IDLE bit to generate ESCI receiver
CPU interrupt requests. Reset clears the ILIE bit.
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
TE — Transmitter Enable Bit
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic 1s from the transmit shift register to the
TxD pin. If software clears the TE bit, the transmitter completes any
transmission in progress before the TxD returns to the idle condition
(logic 1). Clearing and then setting TE during a transmission queues
an idle character to be sent after the character currently being
transmitted. Reset clears the TE bit.
1 = Transmitter enabled
0 = Transmitter disabled
NOTE: Writing to the TE bit is not allowed when the enable ESCI bit (ENSCI) is
clear. ENSCI is in ESCI control register 1.
RE — Receiver Enable Bit
Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver but does not affect receiver interrupt flag bits.
Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
NOTE: Writing to the RE bit is not allowed when the enable ESCI bit (ENSCI) is
clear. ENSCI is in ESCI control register 1.
Technical Data
276
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
Enhanced Serial Communications Interface (ESCI) Module
MOTOROLA