MC68HC908GT16 Datasheet, PDF (369/412 Pages) Motorola, Inc – Microcontrollers

Timer Interface Module (TIM)
Interrupts
22.6 Interrupts
The following TIM sources can generate interrupt requests:
• TIM overflow flag (TOF) — The TOF bit is set when the TIM
counter reaches the modulo value programmed in the TIM counter
modulo registers. The TIM overflow interrupt enable bit, TOIE,
enables TIM overflow CPU interrupt requests. TOF and TOIE are
in the TIM status and control register.
• TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests
are enabled when CHxIE = 1. CHxF and CHxIE are in the TIM
channel x status and control register.
22.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
22.7.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait
mode, the TIM registers are not accessible by the CPU. Any enabled
CPU interrupt request from the TIM can bring the MCU out of wait mode.
If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.
22.7.2 Stop Mode
The TIM is inactive after the execution of a STOP instruction. The STOP
instruction does not affect register conditions or the state of the TIM
counter. TIM operation resumes when the MCU exits stop mode after an
external interrupt.
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
MOTOROLA
Timer Interface Module (TIM)
Technical Data
369